WritingRSSBuild notes from the bench — grouped by project, newest first.NASDAQ ITCH Hardware ParserAug 02, 2026Project ↗Successful Synthesis - Implementation - BitstreamFirst clean Vivado build for the Nexys A7 ITCH pipeline — synthesis, implementation, and bitstream with USE_ETH=1.Aug 01, 2026Project ↗ITCH Ethernet Lab Bring-UpPreparing Nexys A7 Ethernet ingress for end-to-end Mold/ITCH UDP testing on the FPGA market-data pipeline.16-bit MAC Unit (Sky130)Aug 03, 2026Project ↗Reassessing Mac for optimizationReturning to the MAC tapeout path after months on Tomato — planning LibreLane flow, cross-verification, and timing closure.Tomato CPUAug 02, 2026Project ↗Designing Additional BoardsI am pushing to design the remaining boards. I had assumed that the most complicated one to design was the main board — the ALU — which is done and routed (07_alu). The next thi...Jul 31, 2026Project ↗Falling back to 32bIn a rather if not seemingly swing between implementations, I have reconsidered and am falling back to the 32b design. The 40b redesign was intellectually clean — one word type,...Jul 31, 2026Project ↗The lingering thoughtsThe ALU is routed and ready for PCB fabrication. That was the hardest slice of the datapath — three-operand LUT3, carry select, the full combinational core. The lingering proble...Jul 30, 2026Project ↗Redesign into 40b (Old design = 32b)After roughly three months working on Tomato32, the recurring bottleneck has been instruction width, not the ALU itself. Convention says a 32-bit machine gets a 32-bit instructi...Jul 13, 2026Project ↗Architecture UpgradeThe sheer constraint posed by area and available hardware imply that designs that offer more for less are favourable, unlike conventional metrics like parasitic and wiring budge...Jul 13, 2026Project ↗Demo IdeasIt quickly gets abstracted and perhaps indistinguishable from a black box if the final design has no reasonably impressive demo. I've considered a lot of ideas ranging from mode...Jul 13, 2026Project ↗Downgrade for an upgrade - 32b to 16b x 4This ALU has taken several routes since the first abstractions. In the most recent version before this change, I wanted to wire 8 cells of 4b each into a 32b cell. The catch is ...Jul 13, 2026Project ↗Pipelined FPGA - What if...After observing, time is but a monotonic quantity and universal. In current FPGA designs, we program and use, and for another use case, we repeat, In future tomato designs, I am...Jul 13, 2026Project ↗Truth Table LatchIn the current design, the individual cells of tomato may not seem to undergo reprogramming for each operation, given the philosophy it was based off of: what if computers had t...Jun 27, 2026Project ↗Elimination of Mode MultiplexersInitial State & Bottleneck: The previous ALU design utilized a parallel execution model. An incoming signal would split: one path raced through the A/B masking logic into the 74...Jun 16, 2026Project ↗Microcode Control ModularizationThe microcode ROM was always going to be a wiring problem. Every instruction looks up a 64-bit control word: what the ALU should do, whether to write a register, read memory, ju...Jun 15, 2026Project ↗Multiplication and DivisionOne of the biggest hurdles in this build has been implementing hardware multiplication and division. The standard naive approach—sequencing operations to `shift -> add -> accumu...Jun 11, 2026Project ↗Load Store Pipeline AnalysisEvery opcode indexes a 48-bit word in the microcode ROM (`DIG_ROM_256X48_microcodeeeprom`). The fields, confirmed from `main.v:2087–2106`: | Bits | Field | Notes | |------|-----...Jun 10, 2026Project ↗Implementing Mul-Div EngineToday's goal is integrating the multiply-divide engine. I am considering a few ideas. 74xx284/85 can compute the lower and upper products, so I will use them and sequence to com...Aug 01, 2025Project ↗Welcome to Tomato 32This is a build log for Tomato 32. It will keep track of the questions that come up and the answers I settled for. It focussed on build log, the constraints explored and the jou...8-bit Discrete Transistor ALUJun 26, 2026Project ↗ALU Architecture Refinement & Logic OptimizationRefinement of Generate ($G$) and Propagate ($P$) Signals In the initial architecture, the logic generation for the 74182 look-ahead unit was bottlenecked by a naïve implementati...Jun 26, 2026Project ↗ALU - Redesign with 74251In routing the ALU, I came across a realization that the fact that the 125 + 138 combination defeats the optimization i was looking for. In fact, I need 3 chips for a single ALU...Jun 19, 2026Project ↗ALU segment display designFour 32-bit values on screen at once—the three LUT3 operand buses plus the ALU writeback. Each row is eight hex digits; thirty-two seven-segment displays total, live as the data...Mango ToolsAug 01, 2026Project ↗Shell UI - MangoAs the toolkit expands, remembering individual script paths, names, and arguments becomes cumbersome. To solve this, I am introducing Mango—a centralized, interactive shell inte...Aug 01, 2026Project ↗ToolsThis project is a centralized, offline repository designed to replace SaaS platforms (like iLovePDF and online image compressors) entirely. By housing my most frequently used ut...
Aug 02, 2026Project ↗Successful Synthesis - Implementation - BitstreamFirst clean Vivado build for the Nexys A7 ITCH pipeline — synthesis, implementation, and bitstream with USE_ETH=1.
Aug 01, 2026Project ↗ITCH Ethernet Lab Bring-UpPreparing Nexys A7 Ethernet ingress for end-to-end Mold/ITCH UDP testing on the FPGA market-data pipeline.
Aug 03, 2026Project ↗Reassessing Mac for optimizationReturning to the MAC tapeout path after months on Tomato — planning LibreLane flow, cross-verification, and timing closure.
Aug 02, 2026Project ↗Designing Additional BoardsI am pushing to design the remaining boards. I had assumed that the most complicated one to design was the main board — the ALU — which is done and routed (07_alu). The next thi...
Jul 31, 2026Project ↗Falling back to 32bIn a rather if not seemingly swing between implementations, I have reconsidered and am falling back to the 32b design. The 40b redesign was intellectually clean — one word type,...
Jul 31, 2026Project ↗The lingering thoughtsThe ALU is routed and ready for PCB fabrication. That was the hardest slice of the datapath — three-operand LUT3, carry select, the full combinational core. The lingering proble...
Jul 30, 2026Project ↗Redesign into 40b (Old design = 32b)After roughly three months working on Tomato32, the recurring bottleneck has been instruction width, not the ALU itself. Convention says a 32-bit machine gets a 32-bit instructi...
Jul 13, 2026Project ↗Architecture UpgradeThe sheer constraint posed by area and available hardware imply that designs that offer more for less are favourable, unlike conventional metrics like parasitic and wiring budge...
Jul 13, 2026Project ↗Demo IdeasIt quickly gets abstracted and perhaps indistinguishable from a black box if the final design has no reasonably impressive demo. I've considered a lot of ideas ranging from mode...
Jul 13, 2026Project ↗Downgrade for an upgrade - 32b to 16b x 4This ALU has taken several routes since the first abstractions. In the most recent version before this change, I wanted to wire 8 cells of 4b each into a 32b cell. The catch is ...
Jul 13, 2026Project ↗Pipelined FPGA - What if...After observing, time is but a monotonic quantity and universal. In current FPGA designs, we program and use, and for another use case, we repeat, In future tomato designs, I am...
Jul 13, 2026Project ↗Truth Table LatchIn the current design, the individual cells of tomato may not seem to undergo reprogramming for each operation, given the philosophy it was based off of: what if computers had t...
Jun 27, 2026Project ↗Elimination of Mode MultiplexersInitial State & Bottleneck: The previous ALU design utilized a parallel execution model. An incoming signal would split: one path raced through the A/B masking logic into the 74...
Jun 16, 2026Project ↗Microcode Control ModularizationThe microcode ROM was always going to be a wiring problem. Every instruction looks up a 64-bit control word: what the ALU should do, whether to write a register, read memory, ju...
Jun 15, 2026Project ↗Multiplication and DivisionOne of the biggest hurdles in this build has been implementing hardware multiplication and division. The standard naive approach—sequencing operations to `shift -> add -> accumu...
Jun 11, 2026Project ↗Load Store Pipeline AnalysisEvery opcode indexes a 48-bit word in the microcode ROM (`DIG_ROM_256X48_microcodeeeprom`). The fields, confirmed from `main.v:2087–2106`: | Bits | Field | Notes | |------|-----...
Jun 10, 2026Project ↗Implementing Mul-Div EngineToday's goal is integrating the multiply-divide engine. I am considering a few ideas. 74xx284/85 can compute the lower and upper products, so I will use them and sequence to com...
Aug 01, 2025Project ↗Welcome to Tomato 32This is a build log for Tomato 32. It will keep track of the questions that come up and the answers I settled for. It focussed on build log, the constraints explored and the jou...
Jun 26, 2026Project ↗ALU Architecture Refinement & Logic OptimizationRefinement of Generate ($G$) and Propagate ($P$) Signals In the initial architecture, the logic generation for the 74182 look-ahead unit was bottlenecked by a naïve implementati...
Jun 26, 2026Project ↗ALU - Redesign with 74251In routing the ALU, I came across a realization that the fact that the 125 + 138 combination defeats the optimization i was looking for. In fact, I need 3 chips for a single ALU...
Jun 19, 2026Project ↗ALU segment display designFour 32-bit values on screen at once—the three LUT3 operand buses plus the ALU writeback. Each row is eight hex digits; thirty-two seven-segment displays total, live as the data...
Aug 01, 2026Project ↗Shell UI - MangoAs the toolkit expands, remembering individual script paths, names, and arguments becomes cumbersome. To solve this, I am introducing Mango—a centralized, interactive shell inte...
Aug 01, 2026Project ↗ToolsThis project is a centralized, offline repository designed to replace SaaS platforms (like iLovePDF and online image compressors) entirely. By housing my most frequently used ut...