The sheer constraint posed by area and available hardware imply that designs that offer more for less are favourable, unlike conventional metrics like parasitic and wiring budget. Based on that, I've improved the ALU configuration from the original adder(mux(a, b, c), masked invert(b), carry-in)) also f(a, b, c) + g(b), h(carry in) into a more potent design: adder(mux(a, b, c), mux(a, b, c), h(carry in)).
The decision came upon close observation of the earlier g(b) unit. It takes two opcodes and produces 4 states, all of which are generally useful to the context of computing and arithmetic. Take forced 0, which allows the adder to perform f(a, b, c) + 0, in other words, logic mode.
The cost however were two chips, a quad xor gate as global inverter, and a quad Nand gate all for the 4bit requirements of the alu-4b cell. Although two chip counts, I wondered, why not simply replace the "clearly naïve" masked invert and replace with a single 74151 8to1 multiplexer?
Granted, it is one chip, which saves area, and it opens possibilities I never imagined when I first started the earlier ALU design with 19 operations. The catch was obviously the opcode. An 8to1 mux requires 8bit opcode truth table to drive it. To resolve that, I considered, using a 4to1 multiplexer which seemingly perfectly replaces the masked invert with "no catch": with a dual 4to1 multiplexer, I need two to handle 4bit, and requires 4bit to drive it.
The problem there was that true dual 4to1 multiplexer is hard if not impossible to find. 74153, the obvious one of the 74 family is not a true dual mux as the select signals are shared between the internal 4to1 mux. I would have needed 4 chips for that. Also, with 4 chips, the second 4to1 multiplexer inside the chip remains unused, dark silicon consuming area luxury that barely exists for our constraints
If 4 chips are needed for an lut2 (4to1 mux), why not simply build a second multiplexer (lut3), costs two extra chips compared to masked invert and identical chip compared to lut2, but offers astronomical operational space.
I need to acknowledge the operational redundancies offered from the maximum mathematical sample space. For instance, and(a, b, c) + xnor(a, b, c) == xnor(a, b, c) + and(a, b, c). Future progress with clarify the relevant and unique operational space while eliminating Boolean noise.