Tyrone Marhguy
I build computers from discrete transistors to tapeout — and I write the software to test, automate, and deploy them. Currently designing a 32-bit CPU with a focus on flexible datapath control. Previously: full-custom 22nm SRAM, a 1 GbE UDP/IP stack on Artix-7, terminal toolbox so I never upload a PDF to a random website again. The builds are in my projects; the roles, in my experience.
Projects
1 GbE UDP/IP Stack
Deterministic 1 GbE pipeline — RGMII PHY, MAC, ARP/IP/UDP on Artix-7; sub-200 ns RX-to-TX loopback with 100% cocotb coverage.
Tomato — Custom 32-Bit CPU
8-board custom 32-bit computer from discrete logic through PCB tapeout; FPGA prototype at 58 MHz with SymbiYosys formal verification.
16×4 SRAM — Full-Custom Analog Design
Full-custom 6T SRAM macro in 22 nm HP with clocked StrongARM sense amp; 4.571 GHz f_max with NGSpice functional readback.
Recent writing
Reassessing Mac for optimization
Returning to the MAC tapeout path after months on Tomato — planning LibreLane flow, cross-verification, and timing closure.
Designing Additional Boards
I am pushing to design the remaining boards. I had assumed that the most complicated one to design was the main board — the ALU — which is done and routed (07_alu). The next thi...
Successful Synthesis - Implementation - Bitstream
First clean Vivado build for the Nexys A7 ITCH pipeline — synthesis, implementation, and bitstream with USE_ETH=1.