LibreLane
Keeping the chip implementation flow compatible with newer Yosys versions, and making synthesis errors count correctly.
Released in 3.0.8Released in 3.0.10Tyrone Marhguy
I build computers
from first principles.
Computer Engineering junior at the University of Pennsylvania. I design processors, build the hardware, and write the software that runs on them. My independent 32-bit computer is Tomato.
Engineering work & roles: Aragorn AI, Inc. · Vero Electric.
Philadelphia, PA
01 / The independent buildArchitecture / boards / software
Meet Tomato.
A computer of my own.
It started with a question: could I build a computer from individual transistors? That became an ALU, a rethink, and a 32-bit architecture. Today, my FPGA implementation boots TomatoOS and runs games over HDMI. I’m building the discrete machine board by board.
Expressions run left to right. Lines connect discrete examples; this is not a scaling or timing curve.
See all ten expressions and their instruction sequencesThe idea inside the machineChange the logic.
Change the logic.
Keep the datapath.
Two programmable truth tables feed one adder. An instruction can combine Boolean logic and arithmetic instead of sending the result back for another operation.
f(A, B, C) + g(A, B, C) + carry
524,288 control configurations = 256 × 256 truth-table pairs × 8 carry selections. Multiple settings can implement the same function; the instruction ROM selects a practical subset.
Try the full 32-bit playgroundA + (B & C)
Base RV32I2 instructions
AND t0, B, C ADD out, A, t0
Tomato Dual-LUT1 ALU evaluation
F = A · G = B & C out = F + G
The mask feeds the adder directly. Both operations share one trip through the ALU.
Illustrative instruction sequences versus ALU evaluations, with operands already available. These counts do not measure CPU cycles or whole-program speed; ISA extensions and implementation choices can change the comparison.
Full comparison & methodologyAn intentionally outsized register fileHalf a Blackwell SM’s
Half a Blackwell SM’s
register capacity.
The discrete register-file design addresses 32,768 × 32-bit locations: 128 KiB of logical storage, with 256 registers visible per instruction window.
Capacity comparison only. Tomato uses banked, mirrored SRAM; a GPU SM has different porting, bandwidth, latency, and scheduling. This is a design specification, not a GPU performance claim.
A decision from the build logI widened the design.
I widened the design.
Then went back to 32 bits.
A 40-bit instruction looked clean on paper. It also meant wider fields and more board work. I returned to 32 bits so the design could move forward on the bench.
The journal follows the reasoning: what I tried, what complicated the hardware, and what changed.
Read the architectural rethink02 / Beyond my own workbench
I also fix the tools I build with.
OpenROAD
A parser fix for technology files with trailing whitespace, so valid LEF58 input can load.
Inspect the patchVerilator
Using peak resident memory for Linux statistics, so reported memory reflects the process’s physical footprint.
Inspect the patch03 / More from the workbench
View allProjects
Open source EDA
Upstream patches in LibreLane, OpenROAD, Verilator, and OpenFPGA — including Yosys compatibility and synthesis-error counting fixes that shipped in LibreLane 3.0.8 and 3.0.10.
16-bit MAC Unit (Sky130)
BFloat16 MAC with FP32 accumulator and 4-cycle streaming I/O; cocotb-verified RTL with a local LibreLane flow targeting SkyWater 130 nm. Shuttle submission is a later milestone.
100 Mbps UDP/IP Stack
Deterministic 100 Mbps RMII pipeline — MAC, ARP/IP/UDP on Nexys A7 Artix-7; sub-200 ns RX-to-TX loopback with 100% cocotb coverage.
16×4 SRAM — Full-Custom Analog Design
Full-custom 6T SRAM macro in 22 nm HP with clocked StrongARM sense amp; 4.571 GHz f_max with NGSpice functional readback.
From the bench
View allRecent writing
Wallpaper, Polish, and the Rest of the Computer
Semester crunch, website polish, and TomatoOS gaining a Ghana wallpaper—2,987 lines locked as a stable desktop.
Virtual Fallback vs AI
I wondered, what is the use of saying hello to tomato and getting a reponse, Hello {firstname}? It is cool, but withers too quickly. It would be completely orthogonal to build a...
Scope Optimization
Whenever I am working on a main proejct, I choose to spend less time turning the other problems into another main proejct. With that, I have observed that the main issue that pr...