Resume

Computer EngineeringUniversity of Pennsylvania

+1 (267) 320-2734tmarhguy@seas.upenn.edulinkedin.com/in/tmarhguygithub.com/tmarhguyPhiladelphia, PA

tmarhguy.com+1 (267) 320-2734tmarhguy@seas.upenn.edulinkedin.com/in/tmarhguygithub.com/tmarhguyPhiladelphia, PA

Education

Experience

to

Vero ElectricHardware & Firmware Engineer

  • Designed/routed a BQ79616 16-channel battery-monitoring front end for a 240 kWh / 120 kW energy-storage system; closed PCB ERC/DRC with zero errors.
  • Developed embedded C/C++ fault-detection and SPI/I2C acquisition firmware; supported board bring-up with oscilloscopes and logic analyzers.

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Aragorn AI, Inc.Software Engineer Intern

  • Contributed to production backend/API-integration workflows for AI services; debugged cross-service issues and documented service interfaces for production integrations.

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Howard University STEM AchieversSTEM Instructor — AR/VR

  • Verizon Innovative Learning summer program — immersive media, AR, and design thinking for rising 6th–8th graders.
  • Taught augmented reality, 3D printing, and digital product modules in Howard’s three-week STEM Achievers camp.
  • Mentored middle school students through design-thinking projects and hands-on technology labs.

to

University of PennsylvaniaTeaching Assistant — CIS 1100: Intro to Programming

  • Authored 50+ Pytest autograding suites for 300+ students; designed edge-case, boundary, and regression coverage for weekly assignment releases.

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Fife-Penn STEM & CS AcademyProgramming & Engineering Instructor

  • Taught Python, Scratch, and introductory engineering concepts in free after-school coding clubs for Philadelphia K-8 students.
  • Designed weekly lesson plans and debugging exercises across partner schools with Penn Engineering peers.

Open Source

Aug. 2026

OpenROAD

  • Fixed ODB LEF58 parser so production tech files with trailing whitespace load (#11107).

Aug. 2026

Verilator

  • Switched Linux peak-memory from VmPeak to VmHWM so --stats matches RSS (~10× less inflation) (#8070).

Aug. 2026

OpenFPGA

  • Aligned direct interconnect docs with XML parser (#2683).
  • Restored contributor guide (#2682).

Skills

ASIC & EDA

LibreLaneOpenLaneOpenROADSky130YosysOpenFPGATclTinyTapeout

Embedded

C/C++Embedded C/C++FSMsSPI/I²CUARTArduino

FPGA & HDL

Digital (Hneemann)Nexys A7SystemVerilogVerilogVivadoXilinx Artix-7BRAMClock Domain CrossingFSMsnextpnrPlace & RouteRISC-V (RV64IM)RTL SynthesisTiming ClosureWishbone B4XDC ConstraintsYosysopenFPGALoaderTcl

Low-Latency & Networking

ARP/IP/UDPAXI4-StreamLAN8720 MDIOMoldUDP64NASDAQ ITCH 5.0RMII / 100 Mbps MAC

PCB & Analog

KiCad6T SRAMElectric VLSINGSpice

Software

GitLinuxPythonBashC/C++FastAPINext.jsPostgreSQLPytestREST APIsTypeScriptDockerSwift

Verification

cocotbPythonSystemVerilogConstrained-RandomFormal VerificationFunctional CoverageGolden-Model ScoreboardsIcarus VerilogPytestQuestaSVASymbiYosysUVMVerilator

References

Professional references available upon request. For press coverage and background, see my Wikipedia article.

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